In recent years, with development of information communication technology, the demand for portable devices such as a cellular phone and a portable information terminal, which have a display unit, increases. Generally, a sufficiently long, continuous time of use is important for the portable device; thus, a liquid crystal display device is widely used for the display unit of the portable device because of its low power dissipation. Conventionally, a transmissive type of the liquid crystal device using a backlight was employed. However, a reflective type of the liquid crystal device using external light without using the backlight has also been developed, thereby achieving lower power dissipation. Then, in recent years, vivid image display as well as high definition is demanded for the liquid crystal display device, so that the demand for the liquid crystal display device using the active matrix driving method that enables more vivid display than a conventional simple matrix method increases. The demand for lower power dissipation of the liquid crystal device is also required for its driving circuit, so that development of the driving circuit with low power dissipation has been actively under way. The driving circuit for the liquid crystal display device using the active matrix driving method will be described below.
The display unit of the liquid crystal display device using the active matrix driving method is typically constituted from a structure that includes a semiconductor substrate, an opposed substrate, and liquid crystals sealed between the two opposed substrates, as is known. Transparent pixel electrodes and thin-film transistors (TFTs) are disposed on the semiconductor substrate. A single transparent electrode is formed on the entire surface of the opposed substrate. By controlling the TFT having a switching function, a predetermined voltage is applied to each pixel electrode. Then, according to a potential difference between each pixel electrode and the electrode of the opposed substrate, transmissivity of the liquid crystal is changed. Then, the liquid crystal having capacitance holds the potential difference and the transmissivity for a predetermined period, thereby displaying an image.
Data lines for sending a plurality of level voltages (gray scale voltages) to be applied to respective pixel electrodes and scanning lines for sending a switching control signal for the TFTs are disposed on the semiconductor substrate. The data lines become capacitive loads due to the capacitances of the liquid crystals sandwiched between the electrode of the opposed substrate and the semiconductor substrate and the capacitances produced at crossings between the data lines and the scanning lines.
FIG. 15 schematically shows a circuit configuration of a typical conventional active matrix type liquid crystal device. Although the display unit includes a plurality of pixels, only an equivalent circuit constituted from one pixel is illustrated in a display unit 801 in FIG. 15, for simplicity. Referring to FIG. 15, the one pixel is composed by a gate line 811, a data line 812, a TFT 814, a pixel electrode 815, a liquid crystal capacitor 816, and a common electrode 817. The gate line 811 is driven by a gate line driving circuit 802, while the data line 812 is driven by a data line driving circuit 803. The gate line 811 and the data line 812 are generally shared by one row of pixels and one column of pixels. The gate line 811 is connected to gate electrodes for a plurality of TFTs in one row of pixels, while the data line 812 is connected to drains (or sources) of a plurality of TFTs in one column of pixels. A source (or drain) of the TFT for the one pixel is connected to the pixel electrode 815.
The grayscale voltage to the respective pixel electrodes is applied via the data line 812, and the grayscale voltage is written in the totality of pixels connected to the data line 812 during one frame period (approximately 1/60 sec). Thus, the data line driving circuit 803 has to drive the data line 812, which is the capacitive load, with a high speed to high voltage accuracy.
As described above, the data line driving circuit 803 needs to drive the data line 812, which is the capacitive load, at high voltage accuracy and at high speed. Further, for an application as the portable device, low power dissipation and area saving are demanded.
Until now, various driving circuits have been proposed as the data line driving circuit. As the driving circuit having the simplest configuration that saves area with a small number of devices, an amplifier circuit as shown in FIG. 16, for example, is known. FIG. 16 shows the amplifier circuit of a voltage follower configuration in which a charging amplifier circuit 20 is combined with a discharging amplifier circuit 30. This amplifier circuit receives the input voltage Vin to perform current amplification for driving an output terminal. The charging amplifier circuit 20 includes a differential unit and an output stage: in the differential unit, a p-channel current mirror circuit 201, 202 is connected to a pair of outputs of an n-channel differential pair 203, 204 driven by a constant current source 205 as a load circuit, and the output stage is composed by p-channel transistor 206 connected between a high-potential power supply VDD and the output terminal 2. Then, a connection node between the drain of the transistor 201 and the drain of the transistor 203 is connected to the control terminal (gate terminal) of the p-channel transistor 206. The control terminals (gate terminals) of the n-channel differential pair 203, 204 constitute a non-inverting input terminal and an inverting terminal, respectively. The control terminals of the n-channel differential pair 203, 204 are connected to an input terminal 1 and the output terminal 2, respectively.
On the other hand, the discharging amplifier circuit 30 includes the differential unit and the output stage: in the differential unit, an n-channel current mirror circuit 301, 302 is connected to a pair of the outputs of a p-channel differential pair 303, 304 driven by a constant current source 305 as the load circuit. The output stage is constituted from an n-channel transistor 306 connected between a low-potential power supply VSS and the output terminal 2. Then, the connection node between the drain of the transistor 301 constituting the output terminal of the differential unit and the drain of the transistor 303 is connected to the control terminal (gate terminal) of an n-channel transistor 306. The control terminals (gate terminals) of the p-channel differential pair 303, 304 constitute the non-inverting input terminal and the inverting input terminal, while the control terminals (gate terminals) of the p-channel differential pair 303, 304 are connected to the input terminal 1 and the output terminal 2, respectively.
Though the driving circuit shown in FIG. 16 has a simple configuration with a small number of devices, each of the operating ranges of the charging amplifier circuit 20 and the discharging amplifier circuit 30 is subject to a constraint. More specifically, when the input voltage Vin to the charging amplifier circuit 20 is around the low-potential power supply VSS, which is lower than the threshold voltage of the n-channel differential pair 203, 204, the n-channel differential pair 203, 204 is turned off. Thus, the output terminal 2 cannot be charged. When the input voltage Vin to the discharging amplifier circuit 30 is within a range from the high-potential power supply VDD to the threshold voltage of the p-channel differential pair 303, 304, the p-channel differential pair 303, 304 is turned off. Thus, the output terminal 2 cannot be discharged.
If voltages (voltages at the input terminal 1) at which transitions of the n-channel differential pair 203, 204 and the p-channel differential pair 303, 304 from an off state to an on state (operable state) take place are set to VL1 and VL2, respectively, the operating range of the charging amplifier circuit 20 is set in the range from the voltage VL1 to the high-potential power supply VDD. In response to the input voltage Vin in this range (VL1≦Vin≦VDD), the charging amplifier circuit 20 can charge and drives the output terminal 2 in a low potential state to the voltage Vin.
The operating range of the discharging amplifier circuit 30 is set in the range from the low-potential power supply VSS to the voltage VL2. In response to the input voltage Vin in this range (VSS≦Vin≦VL2), the discharging amplifier circuit 30 can discharge and drives the output terminal 2 in a high potential state to the voltage Vin.
As described above, the constraints as mentioned above are imposed on the respective operating ranges of the charging amplifier circuit 20 and the discharging amplifier circuit 30.
Accordingly, a voltage between the voltage VL1 and the voltage VL2 is employed as the input voltage Vin to drive the output terminal 2. On the other hand, a configuration as shown in FIG. 17 is known as an operational amplifier that can expand the operating range of the driving circuit in FIG. 16 to a power supply voltage range (refer to Patent Document 1, for example).
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-9-130171 (p.10, FIG. 5)
Referring to FIG. 17, this operational amplifier is constituted from amplifier circuits 62 and 63. Its configuration is the same as the configuration in which loads 209 and 309 are added to the output terminal 2 in FIG. 16. Referring to FIG. 17, same reference characters are assigned to comparable or identical elements, so that a description of the identical elements will be omitted. A transistor 205′ in FIG. 17 is the current source for which a current value is defined by a bias voltage VB1 supplied to its gate terminal (which is a constant current source for supplying driving current to the differential pair of transistors 203 and 204 with their sources connected in common). A transistor 305′ is the current source for which the current value is defined by a bias voltage VB2 supplied to its gate terminal (for supplying driving current to the differential pair 303, 304). One terminals of the loads 209 and 309 are connected to the output terminal 2, while the other terminals are connected to the low-potential power supply VSS and the high-potential power supply VDD, respectively. The bias voltage VB1 is supplied to the load 209, while the bias voltage VB2 is supplied to the load 309. The amplifier circuits 62 and 63 in Patent Document 1 differentially amplify differential input voltages from first and second input terminals. FIG. 17 shows the voltage follower configuration in which the output terminal is feedback and supplied to the inverting input terminal of the differential amplifier circuit, for comparison with the present invention that will be described later. In the operational amplifier shown in FIG. 17, the loads 209 and 309 are made to function as the loads having predetermined resistances, thereby causing the operational amplifier to operate within the power supply voltage range. More specifically, when the input voltage Vin is lower than the voltage VL1 at which the n-channel differential pair 203, 204 does not operate, the load 309 forms a current path between the high-potential power supply VDD and the output terminal 2. Then, through the operation of the amplifier circuit 63, the output terminal 2 is driven to the voltage Vin. When the input voltage Vin is higher than the voltage VL2 at which the p-channel differential pair 303, 304 does not operate, the load 209 forms the current path between the low-potential power supply VSS and the output terminal 2. Then, through the operation of the amplifier circuit 62, the output terminal is driven to the voltage Vin. When the input voltage Vin is in the rage not less than the voltage VL1 nor more than the voltage VL2 at which the n-channel differential pair 203, 204 and the p-channel differential pair 303, 304 both operate, the amplifier circuits 62 and 63 both operate to drive the output terminal to the voltage Vin. The operational amplifier shown in FIG. 17 expands its operating range to the power supply voltage range using the principle described above.
The driving circuit shown in FIG. 16 is the simplest amplifier circuit generally known. If this is used, the especially area saving driving circuit can be realized. Further, since the number of current paths (the paths of current constantly flowing from the power supply VDD to the VSS) is also small, power dissipation is also comparatively small. With respect to FIG. 17 as well, the operational amplifier with the simple configuration is achieved.